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ISE Design Suite 13.2
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Up to 512 bit data width for AXI cache interconnects
Embedded IP
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Production support for XCS6-1L
Pre-production support for the Artix-7 family and XQ5V devices
Embedded IP Highlights
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New AXI PCIe – supporting 6-series only (7 Series support coming in Release
13.3)
New AXI_QuadSPI
New AHB_AXI_Bridge
Size optimizations for AXI4-Lite interconnect in Shared Address / Shared Data
mode
Improvements to AXI4_V6_DDRx read/write arbitration algorithm to improve
throughput
PLBv46_PCI now supports Spartan?-6
For a list of more Embedded IP changes, please see the section Embedded IP under
Important Release Information .
DSP Edition
System Generator for DSP
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Hardware Co-Simulation
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JTAG Co-Simulation support for KC-705 board
Digilent Plugin support for JTAG Hardware Co-simulation (Provides 30%
speed up in configuration and Co-simulation at full speed over Xilinx
Platform USB)
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AXI4 Support
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CIC Compiler v3.0 - increased input width support to 24 bits
Divider Generator v4.0 - increased operand width support to 64 bits
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New Features in Blocks
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First word fall-through option in FIFO
CORE Generator and IP
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CORE Generator? IP with Artix-7 and Virtex-7 XT Support
Limited Access support for the Artix-7 and Virtex-7 XT device families has been added
to a selection of cores in this release. These cores provide Beta support for the Artix-7
and Virtex-7 XT device families. For a comprehensive listing of IP cores supporting
these new device families, click the IP in this Release tab at
http://www.xilinx.com/ipcenter/coregen/updates_13_2.htm .
New IP Cores
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AXI Infrastructure IP
These new cores make it easy to create designs using AXI4, AXI4-Lite or AXI4-
stream interfaces.
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
www.xilinx.com
11
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